The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
In computing, virtualization techniques are used to allow multiple operating systems to simultaneously share processor resources. One such virtualization technique is Single Root I/O Virtualization (SR-IOV), which is described in the PCI-SIG Single Root I/O Virtualization and Sharing Specifications, the disclosures thereof incorporated by reference herein in their entirety. According to SR-IOV, a Peripheral Component Interconnect Express (PCIe) device can appear to be multiple separate physical PCIe devices. For example, a SR-IOV network interface card (NIC) having a single port can have up to 256 virtual functions, with each virtual function representing a respective NIC port.
SR-IOV employs multiple address spaces. That is, the host employs a PCIe address space, while the device employs a device address space. Communication between the host and the device is accomplished using different address apertures for each virtual function. The location and size of the apertures is determined by the host at run time. Within the device, the resources that map to the virtual functions are located at predefined locations in the device address space. The host apertures, having variable location and size, must be mapped to the fixed internal locations of the resources in the device.
One conventional mapping approach employs address translation windows. According to this approach, at least one address translation window is employed for each virtual function. Systems supporting a large number of virtual functions require a large number of address translation windows. Some systems require two or more address translation windows for each virtual function, depending on the number and type of resources to be mapped to each virtual function. In such conventional approaches, the required number of address translation windows can be prohibitively large.